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1 features ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 3.6v) internally organized 16,384 x 8 and 32,768 x 8 2-wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 1 mhz (5v), 400 khz (2.7v, 2.5v) and 100 khz (1.8v) compatibility write protect pin for hardware and software data protection 64-byte page write mode (partial page writes allowed) self-timed write cycle (5 ms max) high reliability ? endurance: one million write cycles ? data retention: 40 years automotive grade, extended temperature and lead-free/halogen-free devices available 8-lead jedec pdip, 8-lead jedec and eiaj soic, 8-lead map, 8-lead tssop and 8-ball dbga2 tm packages description the AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 16,384/32,768 words of 8 bits each. the device?s cascadable feature allows up to 4 devices to share a common 2-wire bus. the device is optimized for use in many industrial and commercial applica- tions where low power and low voltage operation are essential. the devices are available in space-saving 8-lead jedec pdip, 8-lead jedec soic, 8-lead eiaj soic, 8-lead map (24c128), 8-lead tssop and 8-ball dbga2 packages. in addition, the entire family is available in 2.7v (2.7v to 5.5v) and 1.8v (1.8v to 3.6v) versions. 2-wire serial eeproms 128k (16,384 x 8) 256k (32,768 x 8) AT24C128 at24c256 rev. 0670m?seepr?1/04 pin configurations pin name function a0 - a1 address inputs sda serial data scl serial clock input wp write protect nc no connect gnd ground 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-ball dbga2 bottom view vcc wp scl sda a0 a1 nc gnd 1 2 3 4 8 7 6 5 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead map bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 nc gnd
2 AT24C128/256 0670m?seepr?1/04 block diagram absolute maximum ratings* operating temperature................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 AT24C128/256 0670m?seepr?1/04 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/addresses (a1, a0): the a1 and a0 pins are device address inputs that are hard- wired or left not connected for hardware compatibility with other at24cxx devices. when the pins are hardwired, as many as four 128k /256k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). if the pins are left floating, the a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends con- necting the address pins to gnd. write protect (wp): the write protect input, when connected to gnd, allows normal write operations. when wp is connected high to v cc , all write operations to the memory are inhib- ited. if the pin is left floating, the wp pin will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends con- necting the pin to gnd. memory organization AT24C128/256, 128k/256k serial eeprom: the 128k/256k is internally organized as 256/512 pages of 64-bytes each. random word addressing requires a 14/15-bit data word address.
4 AT24C128/256 0670m?seepr?1/04 pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. dc characteristics (1) note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v. symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +1.8v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max units v cc1 supply voltage 1.8 3.6 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 0.2 a v cc = 3.6v 2.0 i sb2 standby current (2.5v option) v cc = 2.5v v in = v cc or v ss 0.5 a v cc = 5.5v 6.0 i sb3 standby current (5.0v option) v cc = 4.5 - 5.5v v in = v cc or v ss 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) -0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 AT24C128/256 0670m?seepr?1/04 ac characteristics notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.5v, 5v), 10 k ? (1.8v) input pulse voltages: 0.3 v cc to 0.7 v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5 v cc 3. the write cycle time of 5 ms only applies to the AT24C128/256 devices bearing the process letter ?b? on the package (the mark is located in the lower right corner on the top side of the package). 4. the AT24C128/256 bearing the process letter ?b? in the package (the mark is located in the lower right corner on the top side of the package), guarantees 1 million write cycle endurance (1.8 - 3.6v). applicable over recommended operating range from t ai = -40 c to +85 c, v cc = +1.8v to +5.5v, cl = 100 pf (unless oth- erwise noted). test conditions are listed in note 2. symbol parameter 1.8-volt 2.5-volt 5.0-volt units min max min max min max f scl clock frequency, scl 100 400 1000 khz t low clock pulse width low 4.7 1.3 0.4 s t high clock pulse width high 4.0 0.6 0.4 s t aa clock low to data out valid 0.1 4.5 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 4.7 1.3 0.5 s t hd.sta start hold time 4.0 0.6 0.25 s t su.sta start set-up time 4.7 0.6 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in set-up time 200 100 100 ns t r inputs rise time (1) 1.0 0.3 0.3 s t f inputs fall time (1) 300 300 100 ns t su.sto stop set-up time 4.7 0.6 0.25 s t dh data out hold time 100 50 50 ns t wr write cycle time 20 or 5 (3) 10 or 5 (3) 10 or 5 (3) ms endurance (1) 25c, page mode 1,000,000 (4) write cycles
6 AT24C128/256 0670m?seepr?1/04 device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only dur ing scl low time periods (refer to data validity timing diagram). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to start and stop definition timing diagram). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowl- edge that it has received each word. standby mode: the AT24C128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
7 AT24C128/256 0670m?seepr?1/04 bus timing (scl: serial cloc k, sda: serial data i/o) write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 AT24C128/256 0670m?seepr?1/04 data validity start and stop definition output acknowledge
9 AT24C128/256 0670m?seepr?1/04 device addressing the 128k/256k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to figure 1). the device address word con- sists of a mandatory one, zero sequence for the first five most significant bits as shown. this is common to all 2-wire eeprom devices. the 128k/256k uses the two device address bits a1, a0 to allow as many as four devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the e eprom will output a zero. if a compare is not made, the device will return to a standby state. data security: the AT24C128/256 has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receip t of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero. the addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (refer to figure 2). pag e wr it e : the 128k/256k eeprom is capable of 64-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must ter- minate the page write sequence with a stop condition (refer to figure 3). the data word address lower 6 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word addres s will ?roll over? and previous data will be overwritten. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero, allowing the read or write sequence to continue.
10 AT24C128/256 0670m?seepr?1/04 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write sele ct bit set to one is clocked in and acknowl- edged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condi- tion (refer to figure 4). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a fol- lowing stop condition (refer to figure 5). sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequential read will con- tinue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 6). figure 1. device address figure 2. byte write
11 AT24C128/256 0670m?seepr?1/04 figure 3. page write notes: (* = don?t care bit) (? = don?t care bit for the 128k) figure 4. current address read figure 5. random read notes: (* = don?t care bit) (? = don?t care bit for the 128k) figure 6. sequential read
12 AT24C128/256 0670m?seepr?1/04 note: for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics table s. AT24C128 ordering information ordering code package operation range AT24C128-10pi-2.7 AT24C128n-10si-2.7 AT24C128w-10si-2.7 AT24C128u2-10ui-2.7 AT24C128y1-10yi-2.7 AT24C128-10ti-2.7 8p3 8s1 8s2 8u2-1 8y1 8a2 industrial temperature (-40 c to 85 c) AT24C128-10pi-1.8 AT24C128n-10si-1.8 AT24C128w-10si-1.8 AT24C128u2-10ui-1.8 AT24C128y1-10yi-1.8 AT24C128-10ti-1.8 8p3 8s1 8s2 8u2-1 8y1 8a2 industrial temperature (-40 c to 85 c) AT24C128n-10su-2.7 AT24C128n-10su-1.8 AT24C128-10tu-2.7 AT24C128-10tu-1.8 8s1 8s1 8a2 8a2 lead-free/halogen-free/ industrial temperature (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footprint, non-leaded, miniature array package (map) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) options -2.7 low-voltage (2.7v to 5.5v) -1.8 low-voltage (1.8v to 3.6v)
13 AT24C128/256 0670m?seepr?1/04 note: for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics table s. at24c256 ordering information ordering code package operation range at24c256-10pi-2.7 at24c256n-10si-2.7 at24c256w-10si-2.7 at24c256u2-10ui-2.7 at24c256-10ti-2.7 8p3 8s1 8s2 8u2-1 8a2 industrial temperature (-40 c to 85 c) at24c256-10pi-1.8 at24c256n-10si-1.8 at24c256w-10si-1.8 at24c256u2-10ui-1.8 at24c256-10ti-1.8 8p3 8s1 8s2 8u2-1 8a2 industrial temperature (-40 c to 85 c) at24c256n-10su-2.7 at24c256n-10su-1.8 at24c256-10tu-2.7 at24c256-10tu-1.8 8s1 8s1 8a2 8a2 lead-free/halogen-free/ industrial temperature (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic) 8u2-1 8-ball, die ball grid array package (dbga2) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) options -2.7 low-voltage (2.7v to 5.5v) -1.8 low-voltage (1.8v to 3.6v)
14 AT24C128/256 0670m?seepr?1/04 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
15 AT24C128/256 0670m?seepr?1/04 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
16 AT24C128/256 0670m?seepr?1/04 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8s2 , 8-lead, 0.209" body, plastic small outline package (eiaj) 10/7/03 8s2 c common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b and c apply to pb/sn solder plated terminal. the standard thickness of the solder layer shall be 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 ? 0? 8? e 1.27 bsc 4 end view side view e b a a1 d e n 1 c e1 ? l top view
17 AT24C128/256 0670m?seepr?1/04 8u2-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u2-1 a 6/24/03 common dimensions (unit of measure = mm) symbol min nom max note 8u2-1, 8-ball, 2.35 x 3.73 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a1 0.15 0.20 0.25 a2 0.40 0.45 0.50 b 0.25 0.30 0.35 d 2.35 bsc e 3.73 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 1. dimension 'b' is measured at the maximum solder ball diameter. this drawing is for general information only. d a side view top view bottom view 8 solder balls 1 a b c d 2 (e1) e a1 ball pad corner (d1) 1. b a1 a2 d a1 ball pad corner e
18 AT24C128/256 0670m?seepr?1/04 8y1 ? map a ? ? 0.90 a1 0.00 ? 0.05 d 4.70 4.90 5.10 e 2.80 3.00 3.20 d1 0.85 1.00 1.15 e1 0.85 1.00 1.15 b 0.25 0.30 0.35 e 0.65 typ l 0.50 0.60 0.70 pin 1 index area d e a a1 b 8 7 6 e 5 l d1 e1 pin 1 index area 1 2 34 a top view end view bottom view side view 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y1, 8-lead (4.90 x 3.00 mm body) msop array package (map) y1 c 8y1 2/28/03 common dimensions (unit of measure = mm) symbol min nom max note
19 AT24C128/256 0670m?seepr?1/04 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, toler ances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
printed on recycled paper. 0670m?seepr?1/04 xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2004 . all rights reserved. atmel ? and combinations thereof, are the registered trademarks, and dbga2 ? is the trademark of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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